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Computer Engineer Expert Witness

Keywords

Engineering, Circuit Design, Memory Technology Analyst, Computer DRAM Intellectual Property, Computer Intel, Computer Octel S3, Computer Transmeta, Computer Netlist, Computer SimpleTech, Computer US Modular, JEDEC Computer Standards, Computer DDR DRAM Device Development, Computer DDR DRAM Module Development, Circuit Design Patent, Circuit Packaging Patent, Computer Industry, Graphics Architecture Specialist, Diagnostic and Firmware Engineer, Hardware and Software Engineer,

California

Expert Witness No. 3

California

Work History

2007-Present
Memory Technology Analyst

2007
Vice President, Engineering

2005-2007
Vice President, DRAM Technology

2003-2005
Senior Technologist

2002- 2003
Memory Technology

1997-2002
Technology Analyst

1995-1997
Graphic Archictecture Specialist

1989-1995
Field Applications Engineer

1988-1989 Diagnostic and Firmware Engineer

1976-1988 Hardware and Software Engineer

Objective

Technology analysis, marketing, and evangelism or business development position for a company with a sense of mission. I enjoy both daily challenges and long term goals. Affecting the industry and the world in a positive way is a must.

Major Accomplishments

Expert witness for two major intellectual property lawsuits including testimony in FTC case.
Introduced SSD standardization into JEDEC.
Defined architecture of DDR3 Registered DIMM.
Drove international standardization of 4 rank memory modules.
Coordinated JEDEX trade show, doubling attendance over the previous event.
Successfully defined and positioned DDR SDRAM against Direct RDRAM.
Defined and drove into production all DDR small form factor memory modules.
Negotiated agreements to include PCI and PCMCIA in Apple computers.
Technical half of Intel'™s top Flash memory sales team.
Chief architect for an integrated software version control and build management project.
Chief architect for a corporate bug tracking database.

International Standards

JEDEC Board of Directors.
JEDEC DRAM Parametrics Committee.
JEDEC DRAM Packaging Committee.
JEDEC Small Modules Committee.
JEDEC Module Interconnect Committee.
JEDEC Task Groups for Double Data Rate SO-DIMM, Micro-DIMM, Mini-DIMM, SPD, Module Labels.
JEDEC DDR1&2 AC Parametrics Task Group.
JEDEC liaison to Japan'™s standards organization, JEITA.
Delegate to Chinese government for adoption of JEDEC standards.

Marketing and Applications Engineering

Responsible for S3 customer relationships in US and Asia, driving customer requirements into product definition.
Drove the use of intranets as a sales and marketing communications foundation at Intel, S3, and at Transmeta.
Drove long range strategic planning for the home computer market for S3.
Intel account manager for General Magic, Go, and Zenith ATC.
Supported Apple, selling them their first Intel microprocessors.
Negotiated Intel and Apple cooperation on PCI and PCMCIA.

Software Projects

Authored Serial Presence Detect (SPD) interpreter for A Code Morphing Software.
Created system diagnostic test monitor and system boot code for Octel'™s voice mail system.
Chief architect and program manager for bug tracking database and integrated build & version control system.

Hardware Projects

Assisted in development of Transmeta Crusoe DDR interface.
Member of hardware design team for processor emulators and for a voice mail system.
Designed interface simulator for a processor emulator to allow manufacturing test of the system interfaces.
Designed interface simulator for a personal computer to automate manufacturing test of all electrical interfaces.

Awards

Available upon request.

Patents

Available upon request.

Teaching and Public Speaking

Available upon request.

Publications

Available upon request.

Education

Oregon Graduate Center, Computer Sciences
University of Portland, Computer Sciences
Mission College, Personal Fitness Trainer

References supplied upon request.

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