1980 Engineering Degree: Material Science Engineering
1978 MS Material Science and Engineering
1977 BS Material Science And Engineering
1993 - present Semiconductor Consultant
Consulting in various aspects of semiconductor technology and semiconductor manufacturing including expert technical consultations in ITC and Civil litigation.
1989 – 1993 Maxim Integrated Products
Personally developed a high voltage BICMOS process, introduced it to production, and proved the feasibility of adding an EEPROM element to it. Established MAXIM processes in a newly purchased fab, developed the company’s newest analog process, installed MAXIM’s production process in a new foundry, and managed the relationship.
1983 –1989 Advanced Micro Devices
Managed consolidation of test chip development through the building of a company-wide standard test chip library. As a direct result of this project, the time needed to build test chips was reduced by 60%, structures were improved, and test program generation was accelerated. Contributed to development of 256k SRAM, including process flow, a backend planarization scheme, and overseeing the building of generic test chip library. Participated in defining 1M CMOS DRAM process and proved feasibility of integrating trenches in the process. Coordinated the development of post groove planarization process and double poly module. The project ended successfully with a working first silicon. Developed and proved feasibility of integrating EEPROM with DRAM CMOS process and devices Reduced cell size by 40%, process steps by 15%, and improved EEPROM programming operation.
1982 - 1983 American Microsystems, Inc.
Introduced and established the EEPROM process. Directed the design of the test chip, process flow determination, manufacture of several working runs and measurement of the electrical parameters. Created a new process approach that improves poly dielectric strength and founded a new cell structure with multiple benefits over existing cells.
1980 – 1982 INTEL
Participated in the development of EEPROM technology with particular emphasis on the process reliability aspects such as charge retention and cycling endurance. Work involved the study of failure mechanisms, making the necessary process changes, and evaluating the results. Regular interaction with fab and technology development was required. Improved operator utilization by 20%.
1978 - 1980 Stanford University
E.E. research group on metallic impurities and their electrical behaviors, Independent research included manufacturing of Si devices and electrical measurements of their properties.
Hands-On Skills and Areas of Expertise in Semiconductor Fabrication
Process Steps Development
Process flow design
Gate and polysilicon oxidation steps
Etching, deposition and planarization process steps
Plasma and Trench etching steps
Wafer gettering methods
pMOS, nMOS, and CMOS process
High voltage BICMOS process
DRAM memory cells
SRAM memory cells
EEPROM memory cells
Precision resistors and capacitors
Transistors/ resistors/capacitors/JFET in pMOS, nMOS, CMOS, and BICMOS processes
Polysilicon - polysilicon capacitors
PNP and NPN transistors
Test Chip Development
Created a library of test chip structures for process and device evaluation.
Measured test structures and evaluated their device properties.
Litigation Support & Patent Expertise
Wrote and received several patents for my development work.
Wrote expert reports and served as an expert witness for patent litigation.
Wrote several declarations regarding patent infringements.
Developed a trade secret violation list.
Patent infringement and validity analysis and searches
Actively involved, not purely on a managerial level.
Available upon request
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