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Computer Engineer Circuit Design Memory Technology Analyst Expert Witness

Provides Opinion & Testimony In:

Engineering, Circuit Design, Memory Technology Analyst, Computer DRAM Intellectual Property, Computer Intel, Computer Octel S3, Computer Transmeta, Computer Netlist, Computer SimpleTech, Computer US Modular, JEDEC Computer Standards, Computer DDR DRAM Device Development, Computer DDR DRAM Module Development, Circuit Design Patent, Circuit Packaging Patent, Computer Industry, Graphics Architecture Specialist, Diagnostic Firmware Engineer, Hardware Software Engineer,

 

Expert No. 3

 

SUMMARY

2007-Present  Memory Technology Analyst  Discobolus Designs
2007  Vice President, Engineering US Modular
2005-2007 Vice President, DRAM Technology SimpleTech/STEC
2003-2005 Senior Technologist Netlist
2002- 2003  Memory Technology Analyst Discobolus Designs
1997-2002  Technology Analyst  Transmeta Incorporated
1995-1997 Graphics Architecture Specialist  S3 Incorporated
1989-1995  Field Applications Engineer  Intel Corporation
1988-1989 Diagnostic and Firmware Engineer  Octel Communications
1976-1988 Hardware and Software Engineer Intel Corporation

 

 OBJECTIVE:

Technology analysis, marketing, and evangelism or business development position for a company with a sense of mission. I enjoy both daily challenges and long term goals. Affecting the industry and the world in a positive way is a must.

 

MAJOR ACCOMPLISHMENTS: 

  • Expert witness for two major intellectual property lawsuits including testimony in FTC case.
  • Introduced SSD standardization into JEDEC.
  • Defined architecture of DDR3 Registered DIMM.
  • Drove international standardization of 4 rank memory modules.
  • Coordinated JEDEX trade show, doubling attendance over the previous event.
  • Successfully defined and positioned DDR SDRAM against Direct RDRAM.
  • Defined and drove into production all DDR small form factor memory modules.
  • Negotiated agreements to include PCI and PCMCIA in Apple computers.
  • Technical half of Intel's top Flash memory sales team.
  • Chief architect for an integrated software version control and build management project.
  • Chief architect for a corporate bug tracking database.

 

INTERNATIONAL STANDARDS: 

  • Member, JEDEC Board of Directors.
  • Chairman, JEDEC DRAM Parametrics Committee.
  • Chairman, JEDEC DRAM Packaging Committee.
  • Chairman, JEDEC Small Modules Committee.
  • Chairman, JEDEC Module Interconnect Committee.
  • Chairman, JEDEC Task Groups for Double Data Rate SO-DIMM, Micro-DIMM, Mini-DIMM, SPD, Module Labels.
  • Chairman, JEDEC DDR1&2 AC Parametrics Task Group.
  • JEDEC liaison to Japan's standards organization, JEITA.
  • Delegate to Chinese government for adoption of JEDEC standards.

MARKETING & APPLICATIONS ENGINEERING: 

  • Responsible for S3 customer relationships in US and Asia, driving customer requirements into product definition.
  • Drove the use of intranets as a sales and marketing communications foundation at Intel, S3, and at Transmeta.
  • Drove long range strategic planning for the home computer market for S3.
  • Intel account manager for General Magic, Go, and Zenith ATC.
  • Supported Apple, selling them their first Intel microprocessors.
  • Negotiated Intel and Apple cooperation on PCI and PCMCIA.

 

SOFTWARE PROJECTS: 

  • Authored Serial Presence Detect (SPD) interpreter for Transmeta Code Morphing Software.
  • Created system diagnostic test monitor and system boot code for Octel's voice mail system.
  • Chief architect and program manager for bug tracking database and integrated build & version control system.

HARDWARE PROJECTS: 

  • Assisted in development of Transmeta Crusoe DDR interface.
  • Member of hardware design team for processor emulators and for a voice mail system.
  • Designed interface simulator for a processor emulator to allow manufacturing test of the system interfaces.
  • Designed interface simulator for a personal computer to automate manufacturing test of all electrical interfaces.

AWARDS: 

  • "Technical Achievement Award", JEDEC, 2003
  • "Chairman's Award", JEDEC 2001, 2005.
  • "Contribution Award", AMI2 DDR Summit, 2000.

PATENTS: 

  • "System and Method for Power and Thermal Managed Low Latency Memory Expansion", 
  • "System and Method for Memory Modules Using Direct Die Attach with Through-Board Wire Bonding",
  • "System and Method for Recovering from SDRAM Address Bus Errors", 
  • "High density module having at least two substrates and at least one thermally conductive layer therebetween", 
  • "Registered Dual In-Line Memory Module Having an Extended Register Feature Set", 
  • "High-Density Memory Module Utilizing Low-Density Memory Components", 
  • "Method of Forming a Memory Module Having x8 Organization Using DRAM Devices Having x4 Organization", 
  • "Arrangement of Integrated Circuits in a Memory Module",
  • "Printed circuit board memory module with embedded passive components", 
  • "High Density Memory Module Using Stacked Printed Circuit Boards", 
  • "High Density Memory Module Using Stacked Printed Circuit Boards", 
  • "Vertically Stackable Integrated Circuit", 
  • "System and Method for Self Adjusting Data Strobe",

TEACHING AND PUBLIC SPEAKING:

  • "It's a Green, Green, Green, Green World", Consumer Electronics Show, January 2010
  • "DDR3 Launch Readiness", Panel speaker at Denali Memcon, June 2009
  • "Morphing SSD Into Mainstream Computing Architectures", Flash Summit, April 2009
  • "Merging ATCA and VLP", JEDEC/ATCA August 2007
  • "DDR3 Memory Modules", MemCon, July 2007
  • "Memory Modules for ATCA and AMC", Server Memory Summit, October 2006
  • "DRAM Memory Modules Overview & Future Outlook", JEDEX, April 2006
  • "DRAM Module Market Overview", JEDEX, October 2005
  • "Embedded Resistor Technology for Memory Module Design", IPC, July 2005
  • "Future Vision of Memory Modules for DRAM", JEDEX, April 2005
  • "Very Low Profile Fully Buffered DIMM", JEDEX, April 2005
  • "Embedded Passives in Memory Modules", IMAPS, January 2005
  • "Memory Modules Overview, Spring 2004", JEDEX, April 2004
  • "DDR2 Serial Presence Detect Revision 1.2", JEDEX, April 2004
  • "Serial Presence Detect: Using it Effectively to Improve System Performance", JEDEX, March 2003.
  • "Charge Transfer Model for Input Signaling and Referencing", Timing is Everything Conference, February 2003.
  • "Introduction to DDR", JEDEX Beijing, October 2002.
  • "DDR-II Posted CAS", JEDEX Beijing, October 2002.
  • "DDR Evolution and Memory Market Trends", Smart Modular Sales Conference, September 2002.
  • "Memory Design Considerations That Affect Price and Performance", Platform July 2002 conference.
  • "DDR333 — The Next Wave", JEDEX March 2002 conference.
  • "Low Power Systems Using Transmeta Crusoe Processors", JEDEC March 2002 conference.
  • "Towards the Fanless PC", Platform February 2002 conference.
  • "Moving to 400 MHz and Beyond", Platform February 2002 conference.
  • "Accelerating DRAM Performance", Platform July 2001 conference.
  • "Memory Technology for Small Form Factor Systems", Platform July 2001.
  • "An Analysis of Virtual Channel Memory and Enhanced Memory Technologies", Platform January 2001 conference.
  • "DDR Penetrates Mobile Computing", Platform January 2001 conference.
  • "Double Data Rate SDRAM — The Next Generation", Online Symposium for Electrical Engineers 2001 lecture series.
  • "DDR SDRAM — The Memory of Choice for Mobile Computing", Computex 2000 conference.
  • "Configurations and Considerations for DDR Memory", Platform July 2000 conference.
  • "Memory Solutions for Mobile Platforms", Platform July 2000 conference.
  • "Migrating SDRAM to DDR", Platform 99 and Silicon Tech 99 conferences.
  • "Design of an Engineering Network", 1986 Portland Networking Conference.
  • "A Software Test Coverage Analyzer", 1985 Northwest Quality Conference.
  • In-house and distributor training for S3 computer graphics.
  • Intel University classes on project management, x86 family architecture, UNIX, and C programming.

ARTICLES: 

  • "Four Rank Memory Modules", SimmTester Industry Articles, March 2006
  • "The Industry's Move from Parallel to Serial Interfaces", Denali Memory Report, February 2005.
  • "Charge Transfer Model for SSTL Input Timing", Timing is Everything Newsletter, March 2003.
  • "DDR Takes On Rambus", published as a series in Electronic News, February-April 1999.

EDUCATION: 

  • Oregon Graduate Center, Computer Sciences
  • University of Portland, Computer Sciences
  • Mission College, Personal Fitness Trainer
  • References supplied upon request.

 

 

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