Electronic Design Expert Witness

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Electronic Design Expert Witness

Provides Opinion & Testimony In:

Electronic Design, Motorola, Encoder, Decoder, Radio, Low Power Portable Electronics, CMOS Technology, Analog, USB, USB2, ATA, DDR, COPEC, Intel Chip, Analog Design, Computers, Engineer, Processor, Science, Math,

Expert No. 2644


DBA (on going)
Nova Southeastern University, Herzog School of Business Ft Lauderdale Florida,

MSEE (18 hours) 1976
University of Illinois Champagne/Urbana University (Incomplete moved to Ft Lauderdale)

MBA 1991
Nova Southeastern University, Herzog School of Business Ft Lauderdale Florida, MBA.

BSEE 1972
University of Nebraska, School of Engineering Lincoln Nebraska
University of Miami, MacAurthor School of Engineering Coral Gables Florida Pre Engineering (Freshman Year)
Christopher Columbus Boys Catholic Prep High School, Miami Florida Solitarian (4.0 GPA)

Nov. 2004
Virtuoso AMS Designer Training, Colorado, USA

Dec. 1996
Analog Design Course UCLA

Feb. 2006
University of Colorado Power Electronic Correspondence Course
Advanced Course on Simulink Model building by Mathworks
TI TMS2812 Training
Neo Circuit and DFM Training Cadence (Numerous Intel/Cadence Training courses)

Professional Experience

Honeywell –  Micro Switch
Freeport Ill
Staff Engineer
Design and layout of Hall Effect
LOHET II, ECKO IV, FY Series Proximity Switches.

Motorola Portable Comm
Ft Lauderdale Fla
Portable Products CMOS Design Lead, SCF, Signaling Decoder, Advanced Development Researcher

Motorola Portable Comm
Portable Products CMOS Design Lead, SCF, Signaling Decoder, Advanced Development Researcher

1986 ­1988
Motorola SPS
6805 ASIC Division. CMOS Design Lead. .25u Standard Cell Library

1988 ­1990
MCE Semi ­Conductor
Semiconductor Startup ~ Gate Arrays ~ 200 Custom and Semi ­Custom Ics.

1990 ­1999
Intel Corp
Principle Engineer
Numerous Mixed serial Design Contributions in Seral Links Including USB2, Ethernet ~ 4 Chip Set devices in Solano 815 SDRAM

1999 ­2005
National Semi
COPEC/Advanced Portable Power, Design Center Concentrating on PowerWiseTM Technology LM3230 CMOS RF Controller

2005 ­Retired 2010
Intel Corp
Bangor Analog Power IC and MPU on Chip regulators. Center of Excellence design Lead. Working on Massive Parallel Computing Techniques.

2011 to Present
Aeronautical University
Teaching Senior Graduating engineers for one of the top 5 small Universities in the Nation. Telwecom CEC460, RTOS CEC450

2011 to Present
Expert 2644 Engineering PLLC
Contracts with TriiQuint Semiconductor, doing advanced neural research with ASU Prossor Jennie Si.

Most Important Contributions

1)1985 ­ Motorola Tone Signaling zero crossing encoder/decoder (ESP/Shark Program) Modat, ZVEI etc. First CMOS MPU (COSMAC) based decoder in a Motorola handheld radio.
Significance: Architect and Innovator together with Dave Muri, who radically changed the direction of commercial Low Power Portable Electronics of the time; Transitioning from I2L (bipolar technology) to CMOS using programmable microcontrollers for multi ­standard. Significantly, altered the course of electronics at Motorola and the rest of the industry. The technique was used in Motorola’s flagship handheld MX Radio later in Saber Radio. Established Motorola as the clear leader in all aspects of portable communications. Also awarded Motorola’s first Microprocessor based Patent in the Handheld radio. (Patent #42131 85).This was an Industry first and used common hardware for both the encoder and decoder (all digital zero crossing decoder approach).

2)1988 ­ Manager and Sole designer of BurrBrowns (TI) first Precision 12 bit CMOS MDAC 754 1A in 5u CMOS
Significance: Significantly impacted trends in the adoption of CMOS technology for precision analog products. Previous to this design, 12 bit guaranteed precision was not achievable in standard digital CMOS Technology. The product stood the test of time and is still in production and is in the TI mixed signal data book. (see technical publication #1)

3)1995 ­ Intel’s LeadAnalog Designer Adopting Deep Submicron Analog CMOS technology for Serial Link Communcationi on on the CPU including USB2 and Ethernet on Motherboard and Solano SDRAM Design Lead
Significance: Intel’s analog capabilities were minimal and the pressure to integrated analog capabilities onto the CPU and Chip Sets required significant modification of the design infrastructure (modeling, tools, methodology). Intel being the #1 semiconductor supplier in the world, had the greatest impact on commercial electronics. Integrating precision analog electronics was key to continued market leadership. Direct design contributions were made by Expert 2644 to Ethernet 1 00Mbit , USB and USB2 serial ATA etc including the integration of the first precision bandgap and subbandgap on Intel’s products. These contributions enabled Intel to retain the market leadership in Serial Link Communications on the Motherboard and Chip sets.. In addition, Expert 2644  was the analog design lead for the SDRAM effort in a covert effort within Intel to backup Intel’s stated market position supporting RDRAM. The impact to the industry was estimated at >$1 0B. The success of Solano and the 815/845 allowed Intel to regain market leadership in chip sets and memory interfaces markets. Also Jim architected the first DDR interface using DLL technology on Intel Chip sets.

4)2001 - National Semiconductor Analog Design Lead and COPEC Research Design Center Founder for Powerwise Technology
Significance: Perhaps the most significant impact to National semiconductor’s market direction and image within the electronic sector. The impact is readily observed in the green initiative and National’s stated market direction and product support for PowerWiseTM technology. Jim was instrumental in setting up the ARM, National, Artisan alliance for dynamic closed loop power supply control which is estimated in a savings >50% over conventional dynamic voltage scaling . Jim recruited engineering team and was the senior design lead and acting site technical manager. He designed the LM3230 CMOS PA controller for TriQuint Semiconductor which was the highest margin product in National’s portfolio. This also was the smallest lowest cost GSM EDGE controller in the industry

5)2005- Intel’s NBI Integrated Power Electronics and Massive Parallel Computing Initiative
Significance: NBI formed a integrated power initiative to reduce the cost of platform level solutions in the ATOM or UMPC emerging handheld CPU market segments. Innovative ground breaking techniques were developed including autonomous phase dropping, an industry first which maintains optimum efficiency over all load conditions. Increase to battery life for handheld products incorporating this technology was measured to be greater than 30%. The design was one of the most advanced power controllers in the industry with advanced capabilities including power telemetry reporting, also boot strap startup which allows the power supply controller to be run directly off of a high voltage battery supply with deep submicron processes (>2X the breakdown). Most recently, Jim is the key technical lead on an NBI initiative to bring massive biologically inspired parallel computing using FPGA and GPU technology.


1.IEEE Region #6 Engineer of the Year 2010.
2.Finalist EETimes 2004 EETimes Innovator of the Year for Contributions to Low Power Electronics.
3.2004 10 Most Read and Download JSSC articles. (see publications)
4.Elected Senior Member of IEEE 2002 ­3.
5.Intel Division Recognition Award Intel for USB Contributions 12/18/97
6.MPG Innovator Day 1995 Finalist Intel “New Concepts For Sub ­Micron ESD Protection”
7.Intel Divisional Recognition Award Q1 1997 Assuming Responsibility Far Beyond Job Scope “S - Parameter Characterization”
8.Intel CEG Division Recognition Award for Contributions to GSM Baseband Processor. ACPT2
9.Intel NBI Division Recognition Award 2007 for “Bangor” Intel’s First Integrated Power Regulator Product.
10.Invited Member of Intel’s First Annual Technology Council Meeting 2000
11.Intel Division Recognition Award for Solano 815 Chip Set SDRAM FSB. Acted as the project lead with responsibility for the circuit design of the interface including board and package. Delivered ahead of schedule.
12.Intel Division Recognition Award Camelot “Token Ring” Camelot Project sold to Olicom.
13.Intel Recognition Award for First Pass Success 82570 1 00Mbit Ethernet Chip
14.Intel Division Recognition Award Analog DSP Roadmap Q4 1998
15.Special Recognition for Technical Contributions to 3G (Intel Q3 2001)
16.Intel Division Recognition Award “For excellent Teamwork in Preparing for bangor First Silicon Evaluation of silicon functionality and outstanding Debug support: (Q2 2007)
17.Member National Register of Who’s Who in Executives and Professionals 2004 ­2005
18.Finalist DEG Innovation Contest 2008 presenter “Homogeneous Computing on Heterogeneous Systems”.
19.Nominated Whos Who in America 2003 ­2005
20.SABA Motorola 1988
21.U.S. National Merit Scholar- 1968
22.Renssalaer Award for Science Award for Science and Math Scholarship 1966
23.Miami Herald Runner Up for Silver Knight Award in Mathematics 1967.
24.University of Miami full Early Admission Full Scholarship for Science and Math 1968
25.NROTC Regular Full Scholarship University of Nebraska 1969. Navel Midshipmen Appointment. 1969.

Society Memberships (plus Invited Speaker)

1.Senior Member COMOC Denver Chapter. Invited speaker on CMOS Controller for EDGE PA’s. 2003
2.Senior Member Phoenix Chapter IEEE Circuit Group. 2007.
3.Member FES (Florida Engineering Society) since 1982. Techniques and National SemiConductor PowerWise TM Technology” see Google Expert 2644 Berkeley.
4.Contributor, working group member and contributing author for IEEE 802.3,802.11 later International Standard ISO8802.3 Listed in the author list..
5.Intel Neural network Rodeo 1995 Hosted by ASU and Intel. Televised Presentation on a “Neural Network Analog to Digital Techniques”
6.Numerous working group contributions to IEEE802.3 FDDI, 4T+ Phy and cable standards.
7.Invited Speaker Stanford University for “Standards Convergence between Wired and Wireless” 1996.
8.Professional Engineer, State of Florida , Active in Good standing since 1982

Committee Memberships

1.Active Reviewing Member since 2005 Intel Patent selection Committee for “Circuits” (Held Quarterly)
2.Invited PhD Defense Panelist for Prof Bertan, ASU and Prof Maksimovic University of Colorado.
3.Member of Intel’s First Annual Technology Council Meeting 2000
4.SCR proposal reviewer and coordinator for several Universities (Ohio State, Iowa State, ASU Berkeley.etc) for Intel Corporation.
5.Active IEEE Standards Committee Representative for Intel. 1995 ­2000. 803.3.x Standards (Involved in 5 standardization committees)
6.DEG Intel Senior Technologist Counsel (Grade 10 and Above) Member… .weekly meetings for strategic technology direction and Innovation Review.
7.Invited NASA Innovations Reviewer for Commercial Applications 2008
8.Member and Contributor to COPEC (Colorado Power Electronics Center) since 2001.
9.Invited Speaker 2001: Professor Seth Sanders. Berkeley University Topic: “Low Power Electronics
10.Intel Technical Investment Reviewer 1996. Responsible for technical review of Broadcom Startup Investment. Directly worked with BroadCom on the1 00base4T+ design. Most profitable IPO in the history of electronics.


Available Upon Request

Patents (Over 50 patents through 2011)

Available Upon Request